A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors

Xin Si, Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xiaoyu Sun, Rui Liu 0005, Shimeng Yu, Hiroyuki Yamauchi, Qiang Li 0021, Meng-Fan Chang. A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors. IEEE Trans. on Circuits and Systems, 66(11):4172-4185, 2019. [doi]

Abstract

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