Saroja V. Siddamal, Suhas B. Shirol, Shraddha Hiremath, Nalini C. Iyer. Design and Physical Implementation of Mixed Signal Elapsed Time Counter in 0.18 µm CMOS Technology. In Anirban Sengupta, Sudeb Dasgupta, Virendra Singh, Rohit Sharma, Santosh Kumar Vishvakarma, editors, VLSI Design and Test - 23rd International Symposium, VDAT 2019, Indore, India, July 4-6, 2019, Revised Selected Papers. Volume 1066 of Communications in Computer and Information Science, pages 126-140, Springer, 2019. [doi]
@inproceedings{SiddamalSHI19,
title = {Design and Physical Implementation of Mixed Signal Elapsed Time Counter in 0.18 µm CMOS Technology},
author = {Saroja V. Siddamal and Suhas B. Shirol and Shraddha Hiremath and Nalini C. Iyer},
year = {2019},
doi = {10.1007/978-981-32-9767-8_11},
url = {https://doi.org/10.1007/978-981-32-9767-8_11},
researchr = {https://researchr.org/publication/SiddamalSHI19},
cites = {0},
citedby = {0},
pages = {126-140},
booktitle = {VLSI Design and Test - 23rd International Symposium, VDAT 2019, Indore, India, July 4-6, 2019, Revised Selected Papers},
editor = {Anirban Sengupta and Sudeb Dasgupta and Virendra Singh and Rohit Sharma and Santosh Kumar Vishvakarma},
volume = {1066},
series = {Communications in Computer and Information Science},
publisher = {Springer},
isbn = {978-981-32-9767-8},
}