12 bit 3.072 GS/s 32-way time-interleaved pipelined ADC with digital background calibration for wideband fully digital receiver application in 65 nm complementary metal-oxide-semiconductor

Waleed Hussain Siddiqui, Goang Seong Choi. 12 bit 3.072 GS/s 32-way time-interleaved pipelined ADC with digital background calibration for wideband fully digital receiver application in 65 nm complementary metal-oxide-semiconductor. IET Circuits, Devices & Systems, 14(2):182-191, 2020. [doi]

@article{SiddiquiC20,
  title = {12 bit 3.072 GS/s 32-way time-interleaved pipelined ADC with digital background calibration for wideband fully digital receiver application in 65 nm complementary metal-oxide-semiconductor},
  author = {Waleed Hussain Siddiqui and Goang Seong Choi},
  year = {2020},
  doi = {10.1049/iet-cds.2019.0069},
  url = {https://doi.org/10.1049/iet-cds.2019.0069},
  researchr = {https://researchr.org/publication/SiddiquiC20},
  cites = {0},
  citedby = {0},
  journal = {IET Circuits, Devices & Systems},
  volume = {14},
  number = {2},
  pages = {182-191},
}