Fault modeling for FinFET circuits

Muzaffer O. Simsir, Ajay N. Bhoj, Niraj K. Jha. Fault modeling for FinFET circuits. In Shamik Das, Iris Bahar, Michael T. Niemier, editors, 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010, Anaheim, CA, USA, June 17-18, 2010. pages 41-46, IEEE Computer Society, 2010. [doi]

@inproceedings{SimsirBJ10,
  title = {Fault modeling for FinFET circuits},
  author = {Muzaffer O. Simsir and Ajay N. Bhoj and Niraj K. Jha},
  year = {2010},
  url = {http://dl.acm.org/citation.cfm?id=1835969},
  researchr = {https://researchr.org/publication/SimsirBJ10},
  cites = {0},
  citedby = {0},
  pages = {41-46},
  booktitle = {2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010, Anaheim, CA, USA, June 17-18, 2010},
  editor = {Shamik Das and Iris Bahar and Michael T. Niemier},
  publisher = {IEEE Computer Society},
  isbn = {978-1-4244-8020-3},
}