Shreyas G. Singapura, Rajgopal Kannan, Viktor K. Prasanna. On-chip memory efficient data layout for 2D FFT on 3D memory integrated FPGA. In 2016 IEEE High Performance Extreme Computing Conference, HPEC 2016, Waltham, MA, USA, September 13-15, 2016. pages 1-7, IEEE, 2016. [doi]
Abstract is missing.