Satnam Singh. Design and Verification of CoreConnectTM IP Using Esterel. In Daniel Geist, Enrico Tronci, editors, Correct Hardware Design and Verification Methods, 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L Aquila, Italy, October 21-24, 2003, Proceedings. Volume 2860 of Lecture Notes in Computer Science, pages 283-288, Springer, 2003. [doi]
Abstract is missing.