Modeling location based wafer die yield variation in estimating 3D stacked IC yield from wafer to wafer stacking

Eshan Singh. Modeling location based wafer die yield variation in estimating 3D stacked IC yield from wafer to wafer stacking. In IEEE 32nd VLSI Test Symposium, VTS 2014, Napa, CA, USA, April 13-17, 2014. pages 1-6, IEEE, 2014. [doi]

Authors

Eshan Singh

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