A 1.2v 11b 100Msps 15mW ADC realized using 2.5b pipelined stage followed by time interleaved SAR in 65nm digital CMOS process - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Pratap Narayan Singh, Ashish Kumar, Chandrajit Debnath, Rakesh Malik. A 1.2v 11b 100Msps 15mW ADC realized using 2.5b pipelined stage followed by time interleaved SAR in 65nm digital CMOS process. In Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, CICC 2008, DoubleTree Hotel, San Jose, California, USA, September 21-24, 2008. pages 305-308, IEEE, 2008. [doi]

This author has not been identified. Look up 'Pratap Narayan Singh' in GoogleThis author has not been identified. Look up 'Ashish Kumar' in GoogleThis author has not been identified. Look up 'Chandrajit Debnath' in GoogleThis author has not been identified. Look up 'Rakesh Malik' in Google

runs on WebDSL