Jeevan Sirkunan, Chia Yee Ooi, Nasir Shaikh-Husin, Yuan Wen Hau, Muhammad N. Marsono. Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms. Journal of Systems Architecture, 73:42-52, 2017. [doi]
@article{SirkunanOSHM17,
title = {Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms},
author = {Jeevan Sirkunan and Chia Yee Ooi and Nasir Shaikh-Husin and Yuan Wen Hau and Muhammad N. Marsono},
year = {2017},
doi = {10.1016/j.sysarc.2016.12.006},
url = {http://dx.doi.org/10.1016/j.sysarc.2016.12.006},
researchr = {https://researchr.org/publication/SirkunanOSHM17},
cites = {0},
citedby = {0},
journal = {Journal of Systems Architecture},
volume = {73},
pages = {42-52},
}