Ram Sivaramakrishnan, Sumti Jairath. Next generation SPARC processor cache hierarchy. In 2014 IEEE Hot Chips 26 Symposium (HCS), Cupertino, CA, USA, August 10-12, 2014. pages 1-28, IEEE, 2014. [doi]
@inproceedings{Sivaramakrishnan14,
title = {Next generation SPARC processor cache hierarchy},
author = {Ram Sivaramakrishnan and Sumti Jairath},
year = {2014},
doi = {10.1109/HOTCHIPS.2014.7478828},
url = {https://doi.org/10.1109/HOTCHIPS.2014.7478828},
researchr = {https://researchr.org/publication/Sivaramakrishnan14},
cites = {0},
citedby = {0},
pages = {1-28},
booktitle = {2014 IEEE Hot Chips 26 Symposium (HCS), Cupertino, CA, USA, August 10-12, 2014},
publisher = {IEEE},
isbn = {978-1-4673-8883-2},
}