24.3 A 36.8 2b-TOPS/W self-calibrating GPS accelerator implemented using analog calculation in 65nm LP CMOS

Skylar Skrzyniarz, Laura Fick, Jinal Shah, Yejoong Kim, Dennis Sylvester, David Blaauw, David Fick, Michael B. Henry. 24.3 A 36.8 2b-TOPS/W self-calibrating GPS accelerator implemented using analog calculation in 65nm LP CMOS. In 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016. pages 420-422, IEEE, 2016. [doi]

@inproceedings{SkrzyniarzFSKSB16,
  title = {24.3 A 36.8 2b-TOPS/W self-calibrating GPS accelerator implemented using analog calculation in 65nm LP CMOS},
  author = {Skylar Skrzyniarz and Laura Fick and Jinal Shah and Yejoong Kim and Dennis Sylvester and David Blaauw and David Fick and Michael B. Henry},
  year = {2016},
  doi = {10.1109/ISSCC.2016.7418086},
  url = {http://dx.doi.org/10.1109/ISSCC.2016.7418086},
  researchr = {https://researchr.org/publication/SkrzyniarzFSKSB16},
  cites = {0},
  citedby = {0},
  pages = {420-422},
  booktitle = {2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016},
  publisher = {IEEE},
  isbn = {978-1-4673-9467-3},
}