Evaluating the robustness of secure triple track logic through prototyping

Rafael Soares, Ney Laert Vilar Calazans, Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert. Evaluating the robustness of secure triple track logic through prototyping. In Marcelo Lubaszewski, Michel Renovell, Rajesh K. Gupta, editors, Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008. pages 193-198, ACM, 2008. [doi]

@inproceedings{SoaresCLMTR08,
  title = {Evaluating the robustness of secure triple track logic through prototyping},
  author = {Rafael Soares and Ney Laert Vilar Calazans and Victor Lomné and Philippe Maurine and Lionel Torres and Michel Robert},
  year = {2008},
  doi = {10.1145/1404371.1404425},
  url = {http://doi.acm.org/10.1145/1404371.1404425},
  tags = {logic},
  researchr = {https://researchr.org/publication/SoaresCLMTR08},
  cites = {0},
  citedby = {0},
  pages = {193-198},
  booktitle = {Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008},
  editor = {Marcelo Lubaszewski and Michel Renovell and Rajesh K. Gupta},
  publisher = {ACM},
  isbn = {978-1-60558-231-3},
}