B. Jhnanesh Somayaji, M. S. Bhat. Analysis of implant parameters in high voltage TRIPLE RESURF LDMOS for advanced SoC applications. In Sixth International Symposium on Embedded Computing and System Design, ISED 2016, Patna, India, December 15-17, 2016. pages 72-76, IEEE, 2016. [doi]
Abstract is missing.