Dynamic docking architecture for concurrent testing and peak power reduction - researchr publication authors

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Milind Sonawane, Pavan Kumar Datla Jagannadha, Sailendra Chadalavada, Shantanu Sarangi, Mahmut Yilmaz, Amit Sanghani, Karthikeyan Natarajan, Jonathon E. Colburn, Anubhav Sinha. Dynamic docking architecture for concurrent testing and peak power reduction. In 34th IEEE VLSI Test Symposium, VTS 2016, Las Vegas, NV, USA, April 25-27, 2016. pages 1-6, IEEE Computer Society, 2016. [doi]

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