10-315-MHz Cascaded Hybrid Phase-Locked Loop for Pixel Clock Generation

Minyoung Song, Young-Ho Kwak, Sunghoon Ahn, Hojin Park, Chulwoo Kim. 10-315-MHz Cascaded Hybrid Phase-Locked Loop for Pixel Clock Generation. IEEE Trans. VLSI Syst., 21(11):2080-2093, 2013. [doi]

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