Janusz Sosnowski, Tomasz Wabia, Tomasz Bech. Path Delay Fault Testability Analysis. In 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings. pages 338, IEEE Computer Society, 2000. [doi]
@inproceedings{SosnowskiWB00,
title = {Path Delay Fault Testability Analysis},
author = {Janusz Sosnowski and Tomasz Wabia and Tomasz Bech},
year = {2000},
url = {http://computer.org/proceedings/dft/0719/07190338abs.htm},
tags = {testing, analysis},
researchr = {https://researchr.org/publication/SosnowskiWB00},
cites = {0},
citedby = {0},
pages = {338},
booktitle = {15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings},
publisher = {IEEE Computer Society},
isbn = {0-7695-0719-0},
}