Design and performance of CMOS TSPC cells for high speed pseudo random testing

Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska. Design and performance of CMOS TSPC cells for high speed pseudo random testing. In 14th IEEE VLSI Test Symposium (VTS 96), April 28 - May 1, 1996, Princeton, NJ, USA. pages 368-373, IEEE Computer Society, 1996. [doi]

Abstract

Abstract is missing.