Robert B. Hitchcock Sr.. Partitioning of logic graphs: A theoretical analysis of pin reduction. In Ralph J. Preiss, editor, Proceedings of the 7th Design Automation Workshop, DAC '70, San Francisco, California, USA, June 22-25, 1970. pages 54-63, ACM, 1970. [doi]
@inproceedings{Sr70,
title = {Partitioning of logic graphs: A theoretical analysis of pin reduction},
author = {Robert B. Hitchcock Sr.},
year = {1970},
doi = {10.1145/800160.805112},
url = {http://doi.acm.org/10.1145/800160.805112},
researchr = {https://researchr.org/publication/Sr70},
cites = {0},
citedby = {0},
pages = {54-63},
booktitle = {Proceedings of the 7th Design Automation Workshop, DAC '70, San Francisco, California, USA, June 22-25, 1970},
editor = {Ralph J. Preiss},
publisher = {ACM},
}