Sriseshan Srikanth, Lavanya Subramanian, Sreenivas Subramoney, Thomas M. Conte, Hong Wang. Tackling memory access latency through DRAM row management. In Bruce Jacob, editor, Proceedings of the International Symposium on Memory Systems, MEMSYS 2018, Old Town Alexandria, VA, USA, October 01-04, 2018. pages 137-147, ACM, 2018. [doi]
@inproceedings{SrikanthSSCW18,
title = {Tackling memory access latency through DRAM row management},
author = {Sriseshan Srikanth and Lavanya Subramanian and Sreenivas Subramoney and Thomas M. Conte and Hong Wang},
year = {2018},
doi = {10.1145/3240302.3240314},
url = {https://doi.org/10.1145/3240302.3240314},
researchr = {https://researchr.org/publication/SrikanthSSCW18},
cites = {0},
citedby = {0},
pages = {137-147},
booktitle = {Proceedings of the International Symposium on Memory Systems, MEMSYS 2018, Old Town Alexandria, VA, USA, October 01-04, 2018},
editor = {Bruce Jacob},
publisher = {ACM},
isbn = {978-1-4503-6475-1},
}