Abstract is missing.
- Design guidelines for high-performance SCM hierarchiesDmitrii Ustiugov, Alexandros Daglis, Javier Picorel, Mark Sutherland, Edouard Bugnion, Babak Falsafi, Dionisios N. Pnevmatikatos. 3-16 [doi]
- A comprehensive memory analysis of data intensive workloads on server class architectureHosein Mohammadi Makrani, Hossein Sayadi, Sai Manoj Pudukotai Dinakarrao, Setareh Rafatirad, Houman Homayoun. 19-30 [doi]
- HUB: hugepage ballooning in kernel-based virtual machinesJingyuan Hu, Xiaokuang Bai, Sai Sha, Yingwei Luo, Xiaolin Wang, Zhenlin Wang. 31-37 [doi]
- Memory failure prediction using online learningXiaoming Du, Cong Li. 38-49 [doi]
- Quantify the performance overheads of PMDKWilliam Wang, Stephan Diestelhorst. 50-52 [doi]
- A load balancing technique for memory channelsByoungchan Oh, Nam Sung Kim, Jeongseob Ahn, Bingchao Li, Ronald G. Dreslinski, Trevor N. Mudge. 55-66 [doi]
- Cooperative NV-NUMA: prolonging non-volatile memory lifetime through bandwidth sharingMohammad Reza Jokar, Lunkai Zhang, Frederic T. Chong. 67-78 [doi]
- GraphIA: an in-situ accelerator for large-scale graph processingGushu Li, Guohao Dai, Shuangchen Li, Yu Wang, Yuan Xie. 79-84 [doi]
- Dynamic fine-grained sparse memory accessesBerkin Akin, Chiachen Chou, JongSoo Park, Christopher J. Hughes, Rajat Agarwal. 85-97 [doi]
- Memory-systems challenges in realizing monolithic computersMeenatchi Jagasivamani, Candace Walden, Devesh Singh, Luyi Kang, Shang Li, Mehdi Asnaashari, Sylvain Dubois, Bruce Jacob, Donald Yeung. 98-104 [doi]
- Main memory latency simulation: the missing linkRommel Sánchez Verdejo, Kazi Asifuzzaman, Milan Radulovic, Petar Radojkovic, Eduard Ayguadé, Bruce Jacob. 107-116 [doi]
- Cocoa: synergistic cache compression and error correction in capacity sensitive last level cachesChao Yan, Russ Joseph. 117-128 [doi]
- Opportunistic compression for direct-mapped DRAM cachesAlaa R. Alameldeen, Rajat Agarwal. 129-136 [doi]
- Tackling memory access latency through DRAM row managementSriseshan Srikanth, Lavanya Subramanian, Sreenivas Subramoney, Thomas M. Conte, Hong Wang. 137-147 [doi]
- Efficient coding scheme for DDR4 memory subsystemsKira Kraft, Deepak M. Mathew, Chirag Sudarshan, Matthias Jung 0001, Christian Weis, Norbert Wehn, Florian Longnos. 148-157 [doi]
- Linking parallel algorithmic thinking to many-core memory systems and speedups for boosted decision treesJames Alexander Edwards, Uzi Vishkin. 161-168 [doi]
- Profile-guided scope-based data allocation methodHugo Brunie, Julien Jaeger, Patrick Carribault, Denis Barthou. 169-182 [doi]
- High-level synthesis for irregular applications: enabling temporally multithreaded accelerators183-184 [doi]
- Achieving transparency mapping parallel applications: a memory hierarchy affairEdgar A. León, Matthieu Hautreux. 185-189 [doi]
- Hardware transactional persistent memoryEllis Giles, Kshitij Doshi, Peter J. Varman. 190-205 [doi]
- HMCTherm: a cycle-accurate HMC simulator integrated with detailed power and thermal simulationZhiyuan Yang, Michael Zuzak, Ankur Srivastava. 209-117 [doi]
- Design space exploration of near memory acceleratorsG. Scott Lloyd, Maya Gokhale. 218-220 [doi]
- Fine-grained data usage analysis by access sampling: seeing the data that is not thereZhizhou Zhang, Chencheng Ye, Rahman Lavaee, Ning Gu, Chen Ding. 221-231 [doi]
- Footprint modeling of cache associativity and granularityHao Luo, Guoyang Chen, Fangzhou Liu, Pengcheng Li, Chen Ding, Xipeng Shen. 232-242 [doi]
- Data-driven spatial localitySvetozar Miucin, Alexandra Fedorova. 243-253 [doi]
- Optically connected and reconfigurable GPU architecture for optimized peer-to-peer accessErik Anderson, Jorge González, Alexander Gazman, Rodolfo Azevedo, Keren Bergman. 257-258 [doi]
- Multi-level memristive voltage divider: programming scheme trade-offsTobias Lieske, Mehrdad Biglari, Dietmar Fey. 259-268 [doi]
- AWGR-based optical processor-to-memory communication for low-latency, low-energy vault accessesSebastian Werner, Pouya Fotouhi, Roberto Proietti, S. J. Ben Yoo. 269-278 [doi]
- Leveraging MLC STT-RAM for energy-efficient CNN trainingHengyu Zhao, Jishen Zhao. 279-290 [doi]
- Memory-system requirements for convolutional neural networksAntara Ganguly, Virendra Singh, Rajeev Muralidhar, Masahiro Fujita. 291-197 [doi]
- PPT-GPU: performance prediction toolkit for GPUs identifying the impact of caches: extended abstractYehia Arafa, Abdel-Hameed A. Badawy, Gopinath Chennupati, Nandakishore Santhi, Stephan Eidenbenz. 301-302 [doi]
- Open2C: open-source generator for exploration of coherent cache memory subsystemsAnastasiia Butko, Albert Chen, David Donofrio, Farzad Fatollahi-Fard, John Shalf. 311-317 [doi]
- Towards detection of modified firmware on solid state drives via side channel analysisDane Brown, T. Owens Walker, Ryan N. Rakvic, Robert W. Ives, Hau T. Ngo, James Shey, Justin A. Blanco. 315-320 [doi]
- Demonstration of superconducting memory for an RQL CPURandall Burnett, Ryan Clarke, Timothy Lee, Harold Hearne, Jacob Vogel, Quentin Herr, Anna Herr. 321-323 [doi]
- Architecting a hardware-managed hybrid DIMM optimized for cost/performanceFrederick A. Ware, Javier Bueno, Liji Gopalakrishnan, Brent Haukness, Chris Haywood, Toni Juan, Eric Linstadt, Sally A. McKee, Steven C. Woo, Kenneth L. Wright, Craig Hampel, Gary Bronner. 327-340 [doi]
- A performance & power comparison of modern high-speed DRAM architecturesShang Li, Dhiraj Reddy, Bruce Jacob. 341-353 [doi]
- A raspberry pi operating system for exploring advanced memory system conceptsPascal Francis-Mezger, Vincent M. Weaver. 354-364 [doi]
- Stake: a coupled simulation environment for RISC-V memory experimentsJohn D. Leidel. 365-376 [doi]
- Driving into the memory wall: the role of memory for advanced driver assistance systems and autonomous drivingMatthias Jung 0001, Sally A. McKee, Chirag Sudarshan, Christoph Dropmann, Christian Weis, Norbert Wehn. 377-386 [doi]