H. C. Srinivasaiah, Navakanta Bhat. Response Surface Modeling of 100nm CMOS Process Technology using Design of Experiment. In 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India. pages 285-290, IEEE Computer Society, 2004. [doi]
No references recorded for this publication.
No citations of this publication recorded.