T. Srinivasan, N. Dhanasekar, M. Nivedita, R. Dhivyakrishnan, A. A. Azeezunnisa. Scalable and Parallel Aggregated Bit Vector Packet Classification Using Prefix Computation Model. In Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 13-17 September 2006, Bialystok, Poland. pages 139-144, IEEE Computer Society, 2006. [doi]
@inproceedings{SrinivasanDNDA06,
title = {Scalable and Parallel Aggregated Bit Vector Packet Classification Using Prefix Computation Model},
author = {T. Srinivasan and N. Dhanasekar and M. Nivedita and R. Dhivyakrishnan and A. A. Azeezunnisa},
year = {2006},
doi = {10.1109/PARELEC.2006.71},
url = {http://doi.ieeecomputersociety.org/10.1109/PARELEC.2006.71},
tags = {classification},
researchr = {https://researchr.org/publication/SrinivasanDNDA06},
cites = {0},
citedby = {0},
pages = {139-144},
booktitle = {Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 13-17 September 2006, Bialystok, Poland},
publisher = {IEEE Computer Society},
isbn = {0-7695-2554-7},
}