T. Srinivasan, N. Dhanasekar, M. Nivedita, R. Dhivyakrishnan, A. A. Azeezunnisa. Scalable and Parallel Aggregated Bit Vector Packet Classification Using Prefix Computation Model. In Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 13-17 September 2006, Bialystok, Poland. pages 139-144, IEEE Computer Society, 2006. [doi]
Abstract is missing.