Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism

Saket Srivastava, Aissa Melouki, Bashir M. Al-Hashimi. Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In 2009 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2009, San Francisco, CA, USA, July 30-31, 2009. pages 43-46, IEEE Computer Society, 2009. [doi]

Abstract

Abstract is missing.