Michal Staniewski, Andrzej Pfitzner. Compact DC model of a JVeSFET transistor with reduced number of empirical parameters. In 22nd International Conference Mixed Design of Integrated Circuits & Systems, MIXDES 2015, Torun, Poland, June 25-27, 2015. pages 470-475, IEEE, 2015. [doi]
@inproceedings{StaniewskiP15,
title = {Compact DC model of a JVeSFET transistor with reduced number of empirical parameters},
author = {Michal Staniewski and Andrzej Pfitzner},
year = {2015},
doi = {10.1109/MIXDES.2015.7208565},
url = {http://dx.doi.org/10.1109/MIXDES.2015.7208565},
researchr = {https://researchr.org/publication/StaniewskiP15},
cites = {0},
citedby = {0},
pages = {470-475},
booktitle = {22nd International Conference Mixed Design of Integrated Circuits & Systems, MIXDES 2015, Torun, Poland, June 25-27, 2015},
publisher = {IEEE},
isbn = {978-8-3635-7807-7},
}