A Latency-Hiding Scheme for Multiprocessors with Buffered Multistage Networks - researchr publication authors

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Per Stenström. A Latency-Hiding Scheme for Multiprocessors with Buffered Multistage Networks. In Viktor K. Prasanna, Larry H. Canter, editors, Proceedings of the 6th International Parallel Processing Symposium, Beverly Hills, CA, USA, March 1992. pages 39-42, IEEE Computer Society, 1992.

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