The following publications are possibly variants of this publication:
- R. Jacob Baker, CMOS Circuit Design, Layout, and Simulation (second ed.), Wiley Interscience & IEEE Press (2005) ISBN 0-471-70055-X Hardcover, pp 1039, plus XXXIIIMile K. Stojcev. mr, 46(7):1214-1215, 2006. [doi]
- Reliability of Computer Systems and Networks: Fault Tolerance, Analysis and Design; Martin L. Shooman. John Wiley and Sons Inc., New York; 2002. Hardcover, pp 528, plus XXIIMile K. Stojcev. mr, 44(8):1275-1276, 2004. [doi]
- Bert Haskell, Portable Electronics Product Design and Development , McGraw Hill, New York (2004) ISBN 0-07-141639-0 Hardcover, pp 372, plus XIIMile K. Stojcev. mr, 48(2):333-334, 2008. [doi]
- Alfredo Benso, Paolo Prinetto, editors, Fault injection techniques and tools for embedded systems reliability and evaluation, Kluwer Academic Publishers, Boston, 2003. Hardcover, pp 241, plus XIV, ISBN 1-4020-7589-8Mile K. Stojcev. mr, 46(8):1396-1397, 2006. [doi]
- Testing Static Random Access Memories: Defects, Fault Models and Test Patterns, Said Hamdioui, Kluwer Academic Publishers, Boston, 2004, Hardcover, pp 221, plus XX, ISBN 1-4020-7752-1Mile K. Stojcev. mr, 45(5-6):1012-1013, 2005. [doi]
- Rohit Kapur, CTL for Test Information of Digital ICs Hardcover. Kluwer Academic Publisher, Boston, 2003. pp 173, plus XI, ISBN 1-4020-7293-7Mile K. Stojcev. mr, 43(7):1171-1172, 2003. [doi]