Mile K. Stojcev. Navabi Zainalabedin, Verilog Digital System Design: Register Transfer Level Synthesis, Testbench, & Verification (second ed.), McGraw Hill, New York (2006) ISBN 0-07-144564-1 Hardcover, pp 384, plus XVI. Microelectronics Reliability, 48(1):167-168, 2008. [doi]
@article{Stojcev08,
title = {Navabi Zainalabedin, Verilog Digital System Design: Register Transfer Level Synthesis, Testbench, & Verification (second ed.), McGraw Hill, New York (2006) ISBN 0-07-144564-1 Hardcover, pp 384, plus XVI},
author = {Mile K. Stojcev},
year = {2008},
doi = {10.1016/j.microrel.2006.04.005},
url = {http://dx.doi.org/10.1016/j.microrel.2006.04.005},
tags = {design},
researchr = {https://researchr.org/publication/Stojcev08},
cites = {0},
citedby = {0},
journal = {Microelectronics Reliability},
volume = {48},
number = {1},
pages = {167-168},
}