A bit-sliced, scalable and unified montgomery multiplier architecture for RSA and ECC

M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas. A bit-sliced, scalable and unified montgomery multiplier architecture for RSA and ECC. In IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007. pages 252-257, IEEE, 2007. [doi]

Abstract

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