Yasuhiro Sugimoto. Linearity and intrinsic gain enhancement techniques using positive feedbacks to realize a 1.2-V, 200-MHz, +10.3-dBm of IIP3 and 7th-order LPF in a 65-nm CMOS. In Proceedings of the 37th European Solid-State Circuits Conference, ESSCIRC 2011, Helsinki, Finland, Sept. 12-16, 2011. pages 95-98, IEEE, 2011. [doi]
@inproceedings{Sugimoto11-1,
title = {Linearity and intrinsic gain enhancement techniques using positive feedbacks to realize a 1.2-V, 200-MHz, +10.3-dBm of IIP3 and 7th-order LPF in a 65-nm CMOS},
author = {Yasuhiro Sugimoto},
year = {2011},
doi = {10.1109/ESSCIRC.2011.6044923},
url = {http://dx.doi.org/10.1109/ESSCIRC.2011.6044923},
researchr = {https://researchr.org/publication/Sugimoto11-1},
cites = {0},
citedby = {0},
pages = {95-98},
booktitle = {Proceedings of the 37th European Solid-State Circuits Conference, ESSCIRC 2011, Helsinki, Finland, Sept. 12-16, 2011},
publisher = {IEEE},
isbn = {978-1-4577-0703-2},
}