Yasuhiro Sugimoto, Tetsuya Iida. A current-mode, 3 V, 20 MHz, 9-bit equivalent CMOS sample-and-hold circuit. In Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, Nippon Convention Center, Chiba, Japan, January 28-31, 1997. pages 685-686, IEEE, 1997. [doi]
Abstract is missing.