Yasuhiro Sugimoto, Kazuma Sakatoh. Circuit Techniques to Enhance Linearity and Intrinsic Gain to Realize a 1.2 V, 200 MHz, +10.3 dBm IIP3 and 7th-Order LPF in a 65 nm CMOS. IEICE Transactions, 96-C(6):867-874, 2013. [doi]
@article{SugimotoS13,
title = {Circuit Techniques to Enhance Linearity and Intrinsic Gain to Realize a 1.2 V, 200 MHz, +10.3 dBm IIP3 and 7th-Order LPF in a 65 nm CMOS},
author = {Yasuhiro Sugimoto and Kazuma Sakatoh},
year = {2013},
url = {http://search.ieice.org/bin/summary.php?id=e96-c_6_867},
researchr = {https://researchr.org/publication/SugimotoS13},
cites = {0},
citedby = {0},
journal = {IEICE Transactions},
volume = {96-C},
number = {6},
pages = {867-874},
}