Design and Implementation of High Throughput and Area Efficient Hard Decision Viterbi Decoder in 65nm Technology

Narayan V. Sugur, Saroja V. Siddamal, Samba Sivam Vemala. Design and Implementation of High Throughput and Area Efficient Hard Decision Viterbi Decoder in 65nm Technology. In 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014. pages 353-358, IEEE, 2014. [doi]

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