A High-Performance 64-bit Adder Implemented in Output Prediction Logic

Sheng Sun, Larry McMurchie, Carl Sechen. A High-Performance 64-bit Adder Implemented in Output Prediction Logic. In 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 14-16 March 2001, Salt Lake City, UT, USA. pages 213-223, IEEE Computer Society, 2001. [doi]

@inproceedings{SunMS01,
  title = {A High-Performance 64-bit Adder Implemented in Output Prediction Logic},
  author = {Sheng Sun and Larry McMurchie and Carl Sechen},
  year = {2001},
  doi = {10.1109/ARVLSI.2001.915562},
  url = {http://doi.ieeecomputersociety.org/10.1109/ARVLSI.2001.915562},
  tags = {logic},
  researchr = {https://researchr.org/publication/SunMS01},
  cites = {0},
  citedby = {0},
  pages = {213-223},
  booktitle = {19th  Conference on Advanced Research in VLSI (ARVLSI 2001), 14-16 March 2001, Salt Lake City, UT, USA},
  publisher = {IEEE Computer Society},
  isbn = {0-7695-1037-X},
}