Tameesh Suri, Aneesh Aggarwal. Improving performance of simple cores by exploiting loop-level parallelism through value prediction and reconfiguration. In Gearold Johnson, Carsten Trinitis, Georgi Gaydadjiev, Alexander V. Veidenbaum, editors, Proceedings of the 6th Conference on Computing Frontiers, 2009, Ischia, Italy, May 18-20, 2009. pages 151-160, ACM, 2009. [doi]
@inproceedings{SuriA09:0,
title = {Improving performance of simple cores by exploiting loop-level parallelism through value prediction and reconfiguration},
author = {Tameesh Suri and Aneesh Aggarwal},
year = {2009},
doi = {10.1145/1531743.1531768},
url = {http://doi.acm.org/10.1145/1531743.1531768},
researchr = {https://researchr.org/publication/SuriA09%3A0},
cites = {0},
citedby = {0},
pages = {151-160},
booktitle = {Proceedings of the 6th Conference on Computing Frontiers, 2009, Ischia, Italy, May 18-20, 2009},
editor = {Gearold Johnson and Carsten Trinitis and Georgi Gaydadjiev and Alexander V. Veidenbaum},
publisher = {ACM},
isbn = {978-1-60558-413-3},
}