Improving performance of simple cores by exploiting loop-level parallelism through value prediction and reconfiguration

Tameesh Suri, Aneesh Aggarwal. Improving performance of simple cores by exploiting loop-level parallelism through value prediction and reconfiguration. In Gearold Johnson, Carsten Trinitis, Georgi Gaydadjiev, Alexander V. Veidenbaum, editors, Proceedings of the 6th Conference on Computing Frontiers, 2009, Ischia, Italy, May 18-20, 2009. pages 151-160, ACM, 2009. [doi]

Abstract

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