Jubee Tada. Performance evaluation of 3-D stacked 32-bit parallel multipliers. SIGARCH Computer Architecture News, 41(5):89-94, 2013. [doi]
@article{Tada13-0,
title = {Performance evaluation of 3-D stacked 32-bit parallel multipliers},
author = {Jubee Tada},
year = {2013},
doi = {10.1145/2641361.2641376},
url = {http://doi.acm.org/10.1145/2641361.2641376},
researchr = {https://researchr.org/publication/Tada13-0},
cites = {0},
citedby = {0},
journal = {SIGARCH Computer Architecture News},
volume = {41},
number = {5},
pages = {89-94},
}