A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers - researchr publication authors

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Jubee Tada, Ryusuke Egawa, Kazushige Kawai, Hiroaki Kobayashi, Gensuke Goto. A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers. In Mitsumasa Koyanagi, Morihiro Kada, editors, 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31 - February 2, 2012. pages 1-6, IEEE, 2011. [doi]

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