A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers

Jubee Tada, Ryusuke Egawa, Kazushige Kawai, Hiroaki Kobayashi, Gensuke Goto. A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers. In Mitsumasa Koyanagi, Morihiro Kada, editors, 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31 - February 2, 2012. pages 1-6, IEEE, 2011. [doi]

@inproceedings{TadaEKKG11,
  title = {A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers},
  author = {Jubee Tada and Ryusuke Egawa and Kazushige Kawai and Hiroaki Kobayashi and Gensuke Goto},
  year = {2011},
  doi = {10.1109/3DIC.2012.6263031},
  url = {http://dx.doi.org/10.1109/3DIC.2012.6263031},
  researchr = {https://researchr.org/publication/TadaEKKG11},
  cites = {0},
  citedby = {0},
  pages = {1-6},
  booktitle = {2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31 - February 2, 2012},
  editor = {Mitsumasa Koyanagi and Morihiro Kada},
  publisher = {IEEE},
  isbn = {978-1-4673-2189-1},
}