A 24 Gbps SerDes transceiver for on-chip networks using a new half-data-rate self-timed 3-level signaling scheme - researchr publication

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Ramy N. Tadros, Abdelrahman H. Ahmed, Maged Ghoneima, Yehea Ismail. A 24 Gbps SerDes transceiver for on-chip networks using a new half-data-rate self-timed 3-level signaling scheme. In 5th International Conference on Energy Aware Computing Systems & Applications, ICEAC 2015, Cairo, Egypt, March 24-26, 2015. pages 1-4, IEEE, 2015. [doi]

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