Sofiène Tahar, Ramayya Kumar. Implementing a Methodology for Formally Verifying RISC Processors in HOL. In Jeffrey J. Joyce, Carl-Johan H. Seger, editors, Higher Order Logic Theorem Proving and its Applications, 6th International Workshop, HUG 93, Vancouver, BC, Canada, August 11-13, 1993, Proceedings. Volume 780 of Lecture Notes in Computer Science, pages 281-294, Springer, 1993.
@inproceedings{TaharK93,
title = {Implementing a Methodology for Formally Verifying RISC Processors in HOL},
author = {Sofiène Tahar and Ramayya Kumar},
year = {1993},
researchr = {https://researchr.org/publication/TaharK93},
cites = {0},
citedby = {0},
pages = {281-294},
booktitle = {Higher Order Logic Theorem Proving and its Applications, 6th International Workshop, HUG 93, Vancouver, BC, Canada, August 11-13, 1993, Proceedings},
editor = {Jeffrey J. Joyce and Carl-Johan H. Seger},
volume = {780},
series = {Lecture Notes in Computer Science},
publisher = {Springer},
isbn = {3-540-57826-9},
}