Process Variability Analysis in Interconnect, Logic, and Arithmetic Blocks of 16-nm FinFET FPGAs

Endri Taka, Konstantinos Maragos, George Lentaris, Dimitrios Soudris. Process Variability Analysis in Interconnect, Logic, and Arithmetic Blocks of 16-nm FinFET FPGAs. TRETS, 14(3), 2021. [doi]

@article{TakaMLS21,
  title = {Process Variability Analysis in Interconnect, Logic, and Arithmetic Blocks of 16-nm FinFET FPGAs},
  author = {Endri Taka and Konstantinos Maragos and George Lentaris and Dimitrios Soudris},
  year = {2021},
  doi = {10.1145/3458843},
  url = {https://doi.org/10.1145/3458843},
  researchr = {https://researchr.org/publication/TakaMLS21},
  cites = {0},
  citedby = {0},
  journal = {TRETS},
  volume = {14},
  number = {3},
}