Noboru Takagi. A Delay Model of Multiple-Valued Logic Circuits Consisting of Min, Max, and Literal Operations. IEICE Transactions, 93-D(8):2040-2047, 2010. [doi]
@article{Takagi10,
title = {A Delay Model of Multiple-Valued Logic Circuits Consisting of Min, Max, and Literal Operations},
author = {Noboru Takagi},
year = {2010},
url = {http://search.ieice.org/bin/summary.php?id=e93-d_8_2040},
tags = {logic},
researchr = {https://researchr.org/publication/Takagi10},
cites = {0},
citedby = {0},
journal = {IEICE Transactions},
volume = {93-D},
number = {8},
pages = {2040-2047},
}