Taiga Takata, Yusuke Matsunaga. An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs. In Fabrizio Lombardi, Sanjukta Bhanja, Yehia Massoud, R. Iris Bahar, editors, Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009. pages 351-356, ACM, 2009. [doi]
Abstract is missing.