A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector

Yung Sern Tan, Kiat Seng Yeo, Chirn Chye Boon, Manh Anh Do. A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector. IEEE Trans. on Circuits and Systems, 59-I(6):1156-1167, 2012. [doi]

Authors

Yung Sern Tan

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Kiat Seng Yeo

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Chirn Chye Boon

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Manh Anh Do

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