A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector

Yung Sern Tan, Kiat Seng Yeo, Chirn Chye Boon, Manh Anh Do. A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector. IEEE Trans. on Circuits and Systems, 59-I(6):1156-1167, 2012. [doi]

Abstract

Abstract is missing.