Chika Tanaka, Keiji Ikeda, Masumi Saitoh. New layout design methodology for monolithically integrated 3D CMOS logic circuits based on parasitics engineering. In 45th European Solid State Device Research Conference, ESSDERC 2015, Graz, Austria, September 14-18, 2015. pages 258-261, IEEE, 2015. [doi]
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