A 22nm 56TOPS/W 6/8-bit Linearly-scalable R-2R Multiply-and-Accumulate Architecture with 2.2ns Latency - researchr publication authors

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Tianwen Tang, Antonio Liscidini. A 22nm 56TOPS/W 6/8-bit Linearly-scalable R-2R Multiply-and-Accumulate Architecture with 2.2ns Latency. In 49th IEEE European Solid State Circuits Conference, ESSCIRC 2023, Lisbon, Portugal, September 11-14, 2023. pages 473-476, IEEE, 2023. [doi]

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