A scalable architecture for low-latency market-data processing on FPGA - researchr publication authors

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Qiu Tang, Majing Su, Lei Jiang, Jiajia Yang, Xu Bai. A scalable architecture for low-latency market-data processing on FPGA. In IEEE Symposium on Computers and Communication, ISCC 2016, Messina, Italy, June 27-30, 2016. pages 597-603, IEEE, 2016. [doi]

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