Qiu Tang, Majing Su, Lei Jiang, Jiajia Yang, Xu Bai. A scalable architecture for low-latency market-data processing on FPGA. In IEEE Symposium on Computers and Communication, ISCC 2016, Messina, Italy, June 27-30, 2016. pages 597-603, IEEE, 2016. [doi]
@inproceedings{TangSJYB16,
title = {A scalable architecture for low-latency market-data processing on FPGA},
author = {Qiu Tang and Majing Su and Lei Jiang and Jiajia Yang and Xu Bai},
year = {2016},
doi = {10.1109/ISCC.2016.7543802},
url = {http://doi.ieeecomputersociety.org/10.1109/ISCC.2016.7543802},
researchr = {https://researchr.org/publication/TangSJYB16},
cites = {0},
citedby = {0},
pages = {597-603},
booktitle = {IEEE Symposium on Computers and Communication, ISCC 2016, Messina, Italy, June 27-30, 2016},
publisher = {IEEE},
isbn = {978-1-5090-0679-3},
}